1. Field of the Invention
The present invention relates to a display device for displaying computer images including characters and figures mainly and television images including natural images mainly and a system thereof and particularly to a display device having a frequency resolution conversion function for an interlace scanning signal such as an NTSC, PAL, SECAM, or high definition television signal or an image information signal in a personal computer and to a display device for displaying video signals under various standards such as various computers under different specifications, various televisions, and video output devices.
2. Description of the Prior Art
Recently, as multi-media have been developed, there are increasing needs for displaying natural images of the NTSC system which are picked up by a household VTR or video camera on a display device for displaying images of a personal computer or work station.
However, although most of horizontal scanning frequencies of video signals of a personal computer are almost 24 kHz or higher, the horizontal scanning frequency of the NTSC system is low such as 15.75 kHz. When the display device side attempts to correspond to the horizontal scanning frequency of 15.75 kHz, the burden of the horizontal deflection circuit increases and the image quality is degraded such as an increase in screen distortion. Therefore, a double conversion process for doubling the horizontal scanning frequency by converting an interlace scanning signal to a sequential scanning signal is being examined.
Conversion to a sequential scanning signal is broadly divided into two systems. One of them is an intra-field scanning line interpolation system for generating interpolation scanning lines using the scanning lines in the same field and the other is an inter-field scanning line interpolation system for generating interpolation scanning lines using the scanning lines between the preceding and subsequent fields.
When the inter-field scanning line interpolation system among these two sequential scanning conversion systems is applied to the motion portion of an image, two fields which are different in time are composed, so that a problem arises that a duplicate image is formed. Therefore, it is necessary to generate interpolation scanning lines for the motion portion of an image by the inter-field scanning line interpolation system.
In the inter-field scanning line interpolation system, there are a single scan line doubler system in which a line memory which can store a video signal of at least one scanning line is installed, and a video signal of the interlace scanning system is written into this line memory in units of one scanning line, and it is read twice every time at a speed two times of that of writing and an operation interpolation system for generating interpolation scanning lines by operations in consideration of weighting of upper and lower scanning lines.
However, in the single scan line doubler system, the resolution in the vertical direction reduces and the image quality may be degraded. Therefore, as disclosed in Japanese Patent Application Laid-Open 3-113977, a proposal that the degradation of the resolution in the vertical direction is suppressed by modifying the vertical deflection circuit on the television set side so as to display the same scanning line which is read two times every time at the same location on the cathode ray tube is made. The aforementioned operation interpolation system is disclosed in Japanese Patent Application Laid-Open 4-157886 and others.
As disclosed in Japanese Patent Application Laid-Open 63-63283, an example that the horizontal scanning frequency is doubled by doubling the field frequency and the vertical deflection circuit is devised so as to prevent the scanning positions of an odd field and the scanning positions of an even field from confusing with each other may be cited.
A method for modifying the vertical deflection circuit in such a conventional apparatus requires a means for switching an output signal of the vertical deflection circuit on the television set side, so that the vertical deflection circuit has an extremely special constitution and the cost goes up.
In the operation interpolation system, it cannot be avoided that the cost is greatly increased due to addition of an operation circuit. Furthermore, scanning lines generated by operations are scanning lines which do not exist in the original video signal, so that the sharpness of an image reduces and the image quality may be degraded on the contrary.
Next, the standard for a video output device such as a computer terminal or a television set will be considered. The specification for a video signal sent from a computer is not standardized at present and the horizontal and vertical scanning frequencies, video display period, video display position, and video flyback time are different, so that a dedicated display device corresponding to each video signal is generally necessary. For a request for displaying suitable images corresponding to various video signals on one display device, there is a multi-scan display available. In this kind of display device (multi-scan display), many active elements are used in the deflection circuit, and the circuit is increased in scale so as to keep the stability and reliability of operation, and as a result, how to produce and adjust the display device easily comes into a problem.
The aforementioned scanning frequency of a video signal is increasing further at present and accordingly, the signal specification to which a display device corresponds is enlarged. Recently, a display device which can display not only the aforementioned computer signals but also video signals such as television (NTSC) signals and Hi-Vision signals has been required. Concretely, as to the horizontal scanning frequency of a video signal, a display device which can correspond to from 15.75 kHz of an NTSC signal to about 90 kHz equal to a high definition image or a signal of the CAD/CAM class (2M pixels) is desired.
When an extremely wide range of frequencies is handled as mentioned above, it is considerably difficult for the conventional prior art to correspond to them. The reason is that to allow corresponding to the scanning frequency of a video signal, the complexity of switching control of the element constant of the deflection circuit and the number of parts increase and the circuit scale also increases so as to ensure the reliability of operation. Furthermore, it becomes difficult to ensure the performance by corresponding to the display image quality and screen distortion characteristic of various video signals. As a result, the number of parts to be adjusted increases and the cost goes up.
As a method to solve such a problem, there is a method available that a frequency resolution conversion circuit for processing a video signal digitally and converting it to a signal at the desired horizontal and vertical scanning frequencies (hereinafter called a scan converter) is used. As an example using such a scan converter, there is a display device described in Japanese Patent Application Laid-Open 6-138834.
A display device having the aforementioned conventional scan converter will be explained hereunder with reference to the accompanying drawing.
FIG. 30 shows a rough configuration example thereof. In FIG. 30, numeral 11 indicates a scan converter, 13 a deflection circuit, 14 a cathode ray tube (CRT), 120 a video processor circuit, 150a, 150b, and 150c a video circuit Rch, a video circuit Gch, and a video circuit Bch respectively, 151 a video output circuit, 1100 an input video signal, 1200 an input synchronizing signal, and 1300 an output synchronizing signal.
An input video signal 1100 under various standards of computers is inputted to the scan converter 11 and sampled by the A/D converter which is a component of the scan converter 11 by the dot clock of the input video signal 1100 which is regenerated from the input synchronizing signal 1200 by the PLL (phase locked loop) circuit which is a component of the scan converter 11. The sampled signal is written into the memory which is a component of the scan converter 11. Thereafter, it is read from the memory by the dot clock at the predetermined frequency which is regenerated by the aforementioned (or another) PLL circuit in accordance with the number of dots displayed within one horizontal scanning period of the synchronizing signal 1300 at the desired frequency and an output video signal 1400 is generated by the D/A converter which is a component of the scan converter 11. Furthermore, the output video signal 1400 from the scan converter 11 is inputted to the video circuits 150a, 150b, and 150c, subjected to the processes such as brightness control and contrast control in the video processor circuit 120 which is a component of the video circuit 150, and amplified to a voltage amplitude which is sufficiently enough to drive the cathode ray tube (CRT) 14 in the video output circuit 151. On the other hand, the output synchronizing signal 1300 from the scan converter 11 is inputted to the deflection circuit 13 and outputted to the cathode ray tube (CRT) 14. Therefore, even if a video signal having a scanning frequency beyond the corresponding range of the deflection circuit 13 is inputted, it is processed by the scan converter 11 and can be displayed on the cathode ray tube (CRT) 14.
In the display device having the aforementioned constitution, an increase in the number of parts of the deflection circuit to be adjusted is suppressed and a video signal within an extremely wide range of scanning frequencies can be handled. However, a display device of a television set (TV) or a high definition television set (HDTV) is often used at a visual distance of about 1 m or more between a user and the display device in a bright environment. Therefore, high display brightness is desirable. On the other hand, since a display device of a computer such as a personal computer or a work station is often used at a short visual distance of less than about 1 m between a user and the display device in an environment that the ambient light is comparatively dim and from a viewpoint of fatigue of eyes and furthermore to ensure the focus performance, the brightness is generally lower than that of a television set (TV) or a high definition television set (HDTV). Therefore, when video signals such as computer signals, television signals, and high definition television signals are displayed on one display device, it is desirable to switch the brightness for the aforementioned reason. However, in the conventional method, the brightness is not switched.
Recently, a system for composing and displaying (window) video signals such as television signals and high definition television signals on a screen of computer images has been required and even a system using the scan converter of the aforementioned conventional example can realize such a request comparatively simply. However, an image such as a television signal or high definition television signal to be displayed on a computer screen and other computer images are conventionally displayed at the same brightness. Even in this case, it is desirable that the brightness of an image of a television signal or a high definition television signal is higher than that of a computer image.
Furthermore, the present state of specifications and standards such as the horizontal and vertical frequencies of these video signals is shown below.
The specification of video signals generated by various computers is not standardized and the horizontal scanning frequency (hereinafter referred to as fH), vertical scanning frequency (hereinafter referred to as fV) video display period, video display position, and video flyback time are different. Therefore, a dedicated display device corresponding to each video signal is generally necessary. To allow one display device to display suitable images corresponding to various video signals, there is a multiscan display device. This multiscan display device uses many active elements in the deflection circuit so as to correspond to video signals under various specifications, and the circuit scale increases so as to keep the stability and reliability of operation, and as a result, a problem arises that it is difficult to manufacture and adjust such a display device.
There are increasing requests for a high resolution and the scanning frequency of a video signal is increasing. As a result, the specification range of a signal to which a display device corresponds is enlarged. Furthermore, in addition to display of computer video signals mentioned above, a display device which can display also television (NTSC) signals and high definition (HD) signals has been required recently. Concretely, from a viewpoint of fH of a video signal, a display device which can correspond to from 15.75 kHz of an NTSC signal to about 110 kHz equal to a high definition image or a signal of the CAD/CAM class (resolution of 1600 dotsxc3x971200 lines) is desired.
It is difficult for the prior art to handle a video signal at a frequency within such an extremely wide range (fH: 15 to 110 kHz). Namely, the complexity of the element constant switching control circuit of the deflection circuit and the number of parts increase and the circuit scale increases so as to ensure the reliability of operation. Furthermore, it becomes difficult to ensure the performance corresponding to the image quality and screen distortion of various video signals. As a result, the number of parts to be adjusted increases and the cost goes up.
As a method to solve such a problem, there is a method available that a frequency resolution conversion circuit for processing a video signal digitally and converting it to a signal at the desired horizontal and vertical scanning frequencies (hereinafter called a scan converter) is used. As an example using this scan converter, there are display devices described in Japanese Patent Application Laid-Open 1-232394 and Japanese Patent Application Laid-Open 6-138834.
The aforementioned conventional display device will be explained hereunder with reference to the accompanying drawing.
FIG. 74 shows a rough configuration example thereof. In FIG. 74, numeral 71 indicates an A/D converter, 72 a memory, 73 a D/A converter, 74 a synchronization separator, 75 a first PLL (phase locked loop) circuit (1), 76 a second PLL circuit (2), 77 a controller, 78 a synchronizing signal generator, and 79 a display.
An input video signal 710 under various specifications which is supplied from a computer or others is inputted to the A/D converter 71 and an input synchronizing signal 712 is separated into an input horizontal synchronizing signal 716 and an input vertical synchronizing signal 717 by the synchronization separator 74. The PLL circuit (1) 75 generates a writing side clock signal 713 which is synchronized with the input horizontal synchronizing signal 716 in phase and has a frequency which is N times (N: a natural number) of the frequency fH of the input horizontal synchronizing signal 716 and supplies it to the A/D converter 71, the memory 72, and the controller 77. The PLL circuit (2) 76 generates a reading side clock signal 714 which is synchronized with the input horizontal synchronizing signal 716 in phase and has a frequency which is M times (M: a natural number) of the frequency fH of the input horizontal synchronizing signal 716 and supplies it to the D/A converter 73, the memory 72, and the controller 77. The A/D converter 71 samples the input video signal 710 by the writing side clock signal 713 and supplies digital data 718 to the memory 72. The memory 72 writes the digital data 718 on the basis of the writing side clock signal 713 and a control signal 720 from the controller 77, reads digital data 719 on the basis of a reading side clock signal 714 and the control signal 720 from the controller 77, and supplies it to the D/A converter 73. The D/A converter 73 converts the digital data 719 to an output video signal 711 on the basis of the reading side clock signal 714 and supplies it to the display 79.
The synchronizing signal regenerator 78 is controlled by the controller 77, generates an output synchronizing signal 715 using a clock supplied from the PLL circuit (2) 76, and supplies it to the display 79.
In a display device having the aforementioned constitution, it is possible to handle a video signal at a scanning frequency within an extremely wide range by suppressing an increase in the number of parts of the deflection circuit to be adjusted. However, when an NTSC signal is displayed on such a display device, a problem arises that the synchronous state becomes unstable. Namely, the signal source of the NTSC system is diversified and for example, the input video signal 710 and the input synchronizing signal 712 which are comparatively stable are obtained from a television broadcast in which the LD (laser disk) and receiving state are satisfactory. However, the input video signal 710 and the input synchronizing signal 712 from a television broadcast in which the VTR and receiving state are not satisfactory become very unstable and signals including a phase and a frequency jitter. When the PLL circuits 75 and 76 generate the writing side clock signal 713 and the reading side clock signal 714 in phase-synchronization with such an input synchronizing signal 712 including a phase and frequency jitter, the jitter component can be absorbed to a certain extent but not absorbed perfectly and the jitter component may be increased. The frequency fWCLK of a writing side clock signal when an NTSC signal is displayed on such a conventional display device is generally 14.3 MHz. The frequency fRCLK of a reading side clock signal is 28.6 MHz or higher. Although it is well known, it is necessary that the clock jitter TJIT when the digital process is performed is {fraction (1/10)} of the clock period or less. Therefore, it is necessary that the clock jitter TJIT of the aforementioned write clock signal is 7 ns or less and the clock jitter TJIT of the reading side clock signal is 3.5 ns or less. This is a case that the frequency fRCLK of a reading side clock signal is subjected to a double conversion process of an NTSC signal. However, it is necessary that the clock jitter TJIT when a K times (K: a natural number) conversion process is executed is 7/K ns or less.
When a signal including a phase and frequency jitter is inputted from a VTR, the necessary value of clock jitter of a writing clock signal can be satisfied. However, the necessary value of clock jitter of a reading clock signal is not satisfied often (particularly when Kxe2x89xa74).
Next, the present state of an art for composing an image into the same field or frame is shown below.
Recently, so-called multi-media services such as VOD (video on demand) services which allow a person to watch a favorite TV program when he feels like it or an electronic encyclopedia using a CD-ROM are popular. In such multi-media services, a television image such as a natural image is often composed and displayed on a computer screen.
Since a computer operator generally looks at characters and figures on a computer display near by it, the brightness is set not so high so that they are easy to see. On the other hand, the brightness of a television image is set comparatively high so that it is seen beautifully.
Therefore, when a television image and a computer image of characters and figures are displayed on a computer display device at the same time, the brightness of the television image becomes lower than that when it is seen on a normal television set and the television image becomes dull. As a result, a means for controlling the brightness level of characters and figures displayed on the screen of the display device and the brightness level of a natural image displayed independently of each other and making only the display portion of the natural image bright is necessary.
Picture in picture for composing and displaying a subscreen of television into a master screen is well known as composing display. For picture in picture, there are a plurality of video signal input systems for a master screen and a subscreen provided in a television set and the amplitude level and DC level are controlled independently for each video signal so that the brightness level of the master screen and the brightness level of the subscreen can be changed independently of each other.
On the hand, the process (composition process) for composing television images such as natural images into computer characters and figures is performed by the software process of computer and a video signal which is composed like this is supplied and displayed on the display device. Therefore, when television images such as natural images are composed and displayed into computer characters and figures, one system of composed video signal is mostly supplied to the display as it is. As a result, in the case of a constitution having a plurality of video signal input systems like picture in picture, it is impossible to control the amplitude level and DC level of a composing screen separately.
An object of the present invention is to solve the aforementioned problems and provide a display device having a frequency resolution conversion function for displaying faithfully to an inputted video signal at low cost with little degradation in image quality due to scanning line interpolation.
Furthermore, another object of the present invention is to provide a display device for suppressing an increase in the number of portions to be adjusted and an increase in cost and handling video signals at scanning frequencies within an extremely wide range and when video signals under various standards, for example, a computer signal and a television signal are inputted, for displaying them at an optimum brightness respectively. By doing this, the brightness of an output image of the present invention which accomplishes the aforementioned first object can be adjusted and strengthened.
Still another object of the present invention is to provide an image display system and an image display device for controlling the level of even a composed video signal independently for each composing image. By doing this, the brightness when the first and second objects mentioned above are accomplished can be adjusted and strengthened partially or for each scanning line.
Still another object of the present invention is to provide a display device for handling video signals at scanning frequencies within an extremely wide range and displaying a satisfactory image even if a signal including a phase and frequency jitter is inputted. By doing this, an unstable input signal and a stable input signal are composed so as to obtain a stable image and the first to third objects mentioned above can be accomplished effectively.
To accomplish the above objects, the present invention has a memory for storing at least one scanning line of an inputted video signal of the interlace scanning system and a means for repeating to read the aforementioned video signal of one scanning line from the memory at a speed which is n (n is an integer of 2 or more) times of the writing speed of the video signal for a period which is 1/n of the writing horizontal scanning period and to stop reading for a period of the remaining (nxe2x88x921)/n horizontal scanning period for each scanning line of one field which is sequentially inputted and reading each scanning line so that the continuous fields interpolate the period of stopping of reading from the memory each other.
More concretely, to solve these problems of the prior arts, in a display device of the present invention which has a frequency resolution conversion circuit for storing at least one scanning line of an inputted video signal of the interlace scanning system in a memory, reading a video signal stored in this memory at a speed that is n times of the input speed, and outputting a video signal at a scanning speed of n times and a display means for displaying a video signal in which the scanning speed is changed, a memory control signal generator for reading a video signal of one scanning line from the memory at a speed which is n times of the video signal writing speed for a period which is 1/n of the writing horizontal scanning period, stopping reading for a period of the remaining (nxe2x88x921)/n horizontal scanning period, reading a video signal of one scanning line from the memory for a horizontal scanning period of 1/n at a speed of n times in the next field for the horizontal scanning period in which reading is stopped in the previous field, and stopping reading for the other horizontal scanning period is installed in the aforementioned frequency resolution conversion means.
Furthermore, in a display device comprising an input means for inputting a first video signal of the interlace scanning system, an input means for inputting a second video signal of the sequential scanning system, a frequency resolution conversion means for converting the scanning speed of the first video signal, a switching means for switching and selectively outputting the first video signal which is subjected to the frequency resolution conversion process and the second video signal, and a display for displaying a video signal outputted from this switching means, a memory for storing a video signal of at least one inputted scanning line and a memory control signal generator for reading a video signal of one scanning line from the memory at a speed which is n times of the video signal writing speed for a period which is 1/n of the writing horizontal scanning period, stopping reading for a period of the remaining (nxe2x88x921)/n horizontal scanning period, reading a video signal of one scanning line from the memory for a horizontal scanning period of 1/n at a speed of n times in the next field for the horizontal scanning period in which reading is stopped in the previous field, and stopping reading for the other horizontal scanning period is installed in the aforementioned frequency resolution conversion means. Or, in a display device comprising an analog to digital converter for converting an inputted video signal of the interlace scanning system to a digital signal, a field memory for storing a video signal in at least one field which is outputted from the analog to digital converter, a dot clock generator circuit for multiplying an input horizontal synchronizing signal of an inputted video signal and generating a dot clock, a write control circuit for controlling writing into the field memory, a read control circuit for controlling reading from the field memory, an output synchronizing signal generator circuit for dividing a dot clock generated by the dot clock generator circuit and generating horizontal and vertical synchronizing signals of output, and a frequency resolution converter for increasing the number of fields by n times so as to increase the horizontal scanning frequency by n times, a read delay circuit for delaying a read start signal from the read control circuit so that a video signal of an even field which is read first from the memory is delayed by one horizontal scanning period is installed.
Or, in a display device comprising an analog to digital converter for converting an inputted video signal of the interlace scanning system to a digital signal, a field memory for storing a video signal in at least one field which is outputted from the analog to digital converter, a dot clock generator circuit for multiplying an input horizontal synchronizing signal of an inputted video signal and generating a dot clock, a write control circuit for controlling writing into the field memory, a read control circuit for controlling reading from the field memory, an output synchronizing signal generator circuit for dividing a dot clock generated by the dot clock generator circuit and generating horizontal and vertical synchronizing signals of output, and a scan converter for increasing the number of fields by n times so as to increase the horizontal scanning frequency by n times, an output vertical synchronizing signal shifting circuit for shifting an output vertical synchronizing signal so that continuous output video signals of the same field are displayed at the same scan line position is installed.
Or, in a display device having a requency resolution conversion circuit for increasing the field frequency of an inputted video signal of the interlace scanning system by n times so as to increase the horizontal scanning frequency by n times, an analog to digital converter for converting an inputted analog video signal to a digital signal, a memory for storing at least one field of a video signal outputted from this analog to digital converter, a digital to analog converter for converting a video signal read from this memory to an analog video signal, a dot clock generator circuit for multiplying a horizontal synchronizing signal of an inputted video signal and generating a dot clock, a write control circuit for generating a write control signal for the memory from a dot clock generated by the dot clock generator circuit and an input horizontal synchronizing signal and a vertical synchronizing signal of an inputted video signal, an output synchronizing signal generator circuit for counting a dot clock generated by the dot clock generator circuit and generating and outputting an output horizontal synchronizing signal and a vertical synchronizing signal at a frequency which is n times of that of the input signal, a field detector circuit for discriminating whether the field is an odd field or an even field from a horizontal synchronizing signal and a vertical synchronizing signal of an inputted video signal and outputting a field detection signal, an output vertical synchronizing signal shifting circuit for shifting and outputting a vertical synchronizing signal outputted from the output synchronizing signal generator circuit in dot clock units generated by the dot clock generator circuit on the basis of the field detection signal, and a read control circuit for controlling reading from the memory on the basis of a dot clock generated by the dot clock generator circuit, an output horizontal synchronizing signal outputted from the output synchronizing signal generator circuit, an output vertical synchronizing signal outputted from the output vertical synchronizing signal shifting circuit, and reading from the memory on the basis of the field detection signal are installed in the frequency resolution conversion circuit.
By doing this, the present invention has the function and operation indicated below.
To read a video signal from the memory at a speed which is n times of the writing speed, the scanning speed of a video signal to be inputted is n times. Furthermore, since a video signal is read in the next field during the period that reading from the memory is stopped in the previous field, an image can be displayed so as to interpolate the period of stopping of reading for each field. By shifting an output vertical synchronizing signal, it is possible to allow the scanning positions of the interpolated field to coincide with those of the original field.
Next, to accomplish the above objects, particularly the second object, the present invention has a means (scan converter) for converting at least one of the frequency and resolution which process an input video signal digitally and convert it to a video signal having the predetermined horizontal and vertical scanning frequencies, a variable gain video output means for varying the amplitude of the aforementioned video signal, and a control means for controlling the gain of the variable gain video output means according to at least one value of the aforementioned frequency and resolution.
More concretely, the display device of the present invention comprises a scan converter for inputting an input video signal or an input synchronizing signal under various standards and converting and outputting it to a video signal at the desired horizontal and vertical scanning frequencies, a video signal processor for inputting an output video signal from the scan converter and performing the video signal process such as brightness control and contrast control for the display device, a variable gain video output circuit for inputting an output signal of the video signal processor, amplifying it up to a signal voltage amplitude which can drive the cathode ray tube (CRT), furthermore changing the gain by a control signal from the scan converter in accordance with the aforementioned input video signal, a deflection circuit for inputting an output synchronizing signal from the scan converter, and a cathode ray tube (CRT) and an image can be displayed at an optimum brightness by changing the gain of the variable gain video output circuit suitably according to a video signal under various standards.
The present invention having this constitution has the function and operation indicated below.
The present invention having the aforementioned constitution can suppress an increase in the number of portions to be adjusted and handle a video signal at a scanning frequency within an extremely wide range. When video signals under various standards, for example, a computer signal and a television signal are inputted, they can be displayed at an optimum brightness respectively. By doing this, in the present invention which accomplishes the first object mentioned above, the brightness of an output image can be strengthened and prevented from reduction.
Next, to accomplish particularly the third object, the present invention can compose n (n is an integer of 1 or more) images in at least one of the field and frame, display an image composed by this composition means, designate the timing of the composition position of up to n image signals among the image signals composed by the composition means, and control at least one of the amplitude level and DC level in the area within at least one composition image of the n images at the designated composition position timing. Namely, the present invention designates the image composition timing on the composed image signal and controls the amplitude level and DC level at the designated image signal timing.
By doing this, the present invention has the operation and function indicated below.
The brightness levels of characters, figures, and natural images displayed on the screen of the image display means can be controlled independently of each other. As a result, television images such as natural images are displayed brightly and finely and computer images such as characters and figures are displayed legibly at a low brightness. By doing this, like the correspondence to the second object mentioned above, in the present invention which accomplishes the first object mentioned above, the brightness of an output image can be strengthened when necessary.
Furthermore, to accomplish particularly the fourth object mentioned above, the present invention realizes an image display system comprising a frequency conversion means for processing an input video signal digitally and converting it to a video signal at the predetermined horizontal and vertical scanning frequencies, a first clock generator circuit for generating a clock in synchronization with an input synchronizing signal, a second clock generator circuit for generating an asynchronizing clock signal, and a selection means for selecting one of the clock generator circuits on the basis of the aforementioned predetermined horizontal and vertical frequencies and generating a clock for the aforementioned digital process. By doing this, when the input signal is a stable signal, the selection means selects a clock in synchronization with this input signal, and when the input signal is an unstable signal, the selection means selects a stable clock which is generated in asynchronization the input signal, and outputs it as a reading side clock. Therefore, a display device which can handle a video signal at a scanning frequency within a wide range has an operation and function that even if an input signal including a phase and frequency jitter is inputted, a satisfactory image can be displayed. The operation of the present invention which accomplishes the first to third objects mentioned above can be realized more effectively.
The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description when read in connection with the accompanying drawings.